The International Technology
Roadmap for Semiconductors predicts that the silicon-based CMOS transistor
technology used by microchips today will run out of steam by the end of the
decade, but IBM Research (Yorktown Heights, N.Y.) has a ready replacement
already on the drawing board: carbon-based transistors.
IBM paved the way for
commercialization of carbon-based semiconductor chips with its dual-gate
bi-layer graphene field-effect transistors.
Just as all organic substances -- including people -- are
based on carbon compounds, so too will the microchip technologies of the
future, according to IBM. Carbon nanotubes, nanowires and quantum dots are
possibilities for the post-silicon era, but pure crystalline sheets of carbon --
called graphene -- are the closest cousin to the pure crystalline sheets of
silicon from which today's chips are made.
Graphene solves the No. 1 problem with today's silicon
chips: Namely, that as we make them smaller and faster, they generate more and
more heat. Carbon, on the other hand, harnesses quantum effects to reverse that
trend, consuming less and less power as chips are made increasingly smaller and
faster.
Graphene sheets also have higher carrier mobilities (the
speed at which electrons are propelled by a given voltage). Carrier mobilities
that are hundreds of times larger than silicon chips should translate into
equally faster chip speeds for graphene.
Unfortunately, in single layers, graphene sheets act more
like a conductor than a semiconductor. Semiconductors have a band gap between
their conductive state and their insulating state, which allows them to be
easily turned on and off. Without a band gap, graphene field-effect transistors
(FETs) have dismal on-to-off current ratios that are hundreds of times smaller
than silicon.
"Graphene outperforms silicon in terms of carrier
mobility, but graphene field-effect transistors have had poor on-to-off current
ratios, typically under 10," says IBM Fellow Phaedon Avouris, who oversees
its carbon-based materials efforts. "Now we have been able to obtain
on-to-off switching ratios of 100 at room temperature, and 2,000 at lower
temperatures using our bi-layer graphene FETs."
The key to enhancing graphene's on-to-off ratios, according
IBM, was its invention of a bi-layer construction method for graphene
transistors. CMOS chips work by suspending a metal gate over a silicon semiconductor
channel, but separating from it by an insulating oxide called a dielectric.
Then by applying a voltage to the gate, the flow of electrons through the
channel can be turned on and off. For graphene, IBM had to design a novel
dual-gate stack with an extra layer of a thin polymer to separate the graphene
from the dielectric. The extra polymer layer enabled IBM to reduce the
scattering of carriers in the graphene, which had formerly been caused by
impurities in the oxide. The resulting double-gate structure also allowed IBM
to generate the higher electric fields that opened up its band gap.
